This invention is in the field of integrated circuits, and is more specifically directed to memory cell construction in electrically erasable programmable read-only memories (EEPROMs).
Non-volatile solid-state read/write memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. A common technology for realizing non-volatile solid-state memory devices, more specifically for realizing electrically erasable programmable “read-only” memory (EEPROM) devices, utilizes “floating-gate” transistors to store the data state. According to this conventional technology, the memory cell transistor is “programmed” by biasing it so that electrons tunnel through a thin dielectric film onto an electrically isolated transistor gate element. The trapped electrons on the floating gate will raise the apparent threshold voltage of the memory cell transistor (for n-channel devices), as compared with the threshold voltage with no electrons trapped on the floating gate. This difference is made apparent by different source-drain conduction under normal transistor bias conditions. Modern EEPROM devices are “erasable” in that the memory cell transistors can be biased to remove the electrons from the floating gate, again by way of a tunneling mechanism. “Flash” memory devices are typically realized by EEPROM memory arrays, in which the erase operation is applied simultaneously to a large number (a “block”) of memory cells.
According to one approach, EEPROM cells are realized by metal-oxide semiconductor (MOS) transistors having two polysilicon gate electrodes. A control gate electrode is electrically connected to decode and other circuitry in the EEPROM integrated circuit, and a floating gate is disposed between the control gate electrode and the channel region of the memory transistor. In this conventional construction, electrons tunnel to the floating gate upon application of a high programming voltage to the control gate (which capacitively couples to the floating gate) relative to the source and drain regions of the memory transistor.
Because of the convenience and efficiency of modern flash EEPROM memories, it is now desirable and commonplace to embed EEPROM memory within larger scale integrated circuits, such as modern complex microprocessors, digital signal processors, and other large-scale logic circuitry. Such embedded EEPROM can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage. On a smaller scale, EEPROM memory cells can be used to realize control registers by way of which a larger scale logic circuit can be configured, and used to “trim” analog levels after electrical measurement. In such embedded applications, a double-level-polysilicon process may not be available for the EEPROM if the embedding logic circuit does not require such a complex structure. As such, EEPROM cells constructed by a single polysilicon level process are known.
FIG. 1a is an electrical schematic of conventional single polysilicon level EEPROM memory cell 1. In this conventional single-poly example, memory cell 1 consists of floating-gate transistor 2, tunneling capacitor 4 and coupling capacitor 6. Floating-gate transistor 2 is an n-channel MOS transistor with source terminal S and drain terminal D; the body node (not shown in FIG. 1a) is generally connected to the transistor source. Floating gate FG is an electrically isolated conductive structure that serves as the gate of transistor 2 and that serves as a plate of each of tunneling capacitor 4 and coupling capacitor 6. Tunneling capacitor 4 is connected between terminal T and floating gate FG, and coupling capacitor 6 is connected between terminal P and floating gate FG.
In this example, transistor 2 is constructed so that it is a depletion mode device (i.e., threshold voltage <0) if no electrons are trapped on floating gate FG. On the other hand, trapped electrons on floating gate FG will raise the threshold voltage of transistor 2 above zero volts, in which case floating gate FG holds transistor 2 off. The presence or absence of source-drain conduction in response to a positive drain-to-source voltage thus depends on whether electrons are trapped on floating gate FG. If transistor 2 is “programmed” (i.e., electrons trapped on floating gate FG), source-drain conduction is zero for a positive drain-to-source voltage. Conversely, if transistor 2 is “erased” (no trapped electrons at floating gate FG), transistor 2 will conduct in response to a positive drain-to-source voltage.
Programming and erase operations are enabled by constructing coupling capacitor 6 to have a much larger capacitance than tunneling capacitor 4, for example at least ten times the capacitance of tunneling capacitor 4. As a result, if a differential voltage is applied at terminal P relative to terminal T, the voltage induced onto floating gate FG will be much closer to the voltage at terminal P than to the voltage at terminal T. This differential voltage will thus primarily appear across tunneling capacitor 4, in which case any electrons that tunnel to and from floating gate FG, as a result of this differential voltage, will do so through tunneling capacitor 4.
FIGS. 1b and 1c are plan and cross-sectional views, respectively, of an example of conventional memory cell 1. Tunneling capacitor 4 is constructed as a polysilicon-to-bulk capacitor, by a portion of polysilicon element 15 overlying n-well 10a at a “moat” region of its surface defined by field oxide structures 16 (FIG. 1c). Diffusion 12a is a heavily doped p-type diffused region formed into this moat region of n-well 10a, in a self-aligned manner relative to polysilicon element 15 as shown in FIG. 1c. Some lateral diffusion of the dopant extends diffusion 12a for a small distance under the edge of polysilicon element 15, as shown. This lateral diffusion enhances the capacitive coupling of tunneling capacitor 4. The size of tunneling capacitor 4 is defined by the area underlying polysilicon element 15 within the moat region of n-well 10a. As shown in the cross-section of FIG. 1c, dielectric film 20 is disposed between polysilicon element 15 and the surface of n-well 10a, and serves as the capacitor dielectric. To enable tunneling of electrons therethrough, dielectric film 20 is a relative thin layer, typically of silicon dioxide or silicon nitride, for example on the order of 80 Å to 150 Å in thickness. N-type diffusion 14a within n-well 10a provides a non-rectifying top-side electrical contact to n-well 10a. Contact openings C indicate the location of conductive contacts through overlying dielectric layers to the diffused regions in the structure of FIG. 1b. For example, terminal T is connected by way of an overlying metal or other conductor level (not shown) through contact openings C in common to diffusions 12a, 14a. As such, p-type diffusion 12a within n-well 10a is at the same potential as n-well 10a itself, serving as the opposing plate of tunneling capacitor 4 from polysilicon element 15.
Coupling capacitor 6 is also a polysilicon-to-bulk capacitor, again with dielectric film 20 serving as the capacitor dielectric at moat regions of the surface of n-well 10b defined by field oxide structures 16. P-type diffused region 12b is defined in n-well 10b in a self-aligned manner relative to polysilicon element 15. Lateral diffusion of p-type region 12b under polysilicon element 15 also enhances capacitive coupling in coupling capacitor 6. N-type diffusion 14b provides a non-rectifying connection to n-well 10b. Terminal P is connected by a metal conductor level (not shown) in common to diffusions 12b, 14b via contact openings C, to set the potential of one plate of coupling capacitor 6. Polysilicon element 15 serves as the other plate of coupling capacitor 6.
Transistor 2 is an n-channel MOS transistor realized by n-type diffusions 14c, 14d within a moat region defined by field oxide structures 16 at the surface of p-well 18 (FIG. 1c). In the conventional manner, n-type diffusions 14c, 14d are formed by n+ source-drain diffusion after the formation of polysilicon element 15, so that transistor 2 is of the self-aligned type (the portion of moat region 14c underlying polysilicon electrode 15 remains p-type, as usual for an n-channel transistor). Dielectric film 20 serves as the gate dielectric for transistor 2, at locations underlying polysilicon element 15. Drain terminal D is connected to n-type diffusion 14c through contact C on one side of polysilicon element 15, and source terminal S is connected to n-type diffusion 14d on another side of polysilicon element 15. P-type diffusion 12c is also defined within p-well 18 to provide contact to the body node of transistor 2 via a corresponding contact C. Typically, this body node contact via p-type diffusion 12c is at the same potential as source terminal S. And as shown in FIG. 1c, n-wells 10a, 10b and p-well 8 are formed at a surface of substrate 19, which is lightly-doped p-type single crystal silicon.
As shown in FIG. 1b, polysilicon element 15 is a single unitary structure that serves as a plate of capacitors 4, 6 and as floating gate FG of transistor 2 in memory cell 1. The area defined by polysilicon element 15 in the moat region of n-well 10b is much larger than that defined by polysilicon element 15 at moat regions of n-well 10a, because of the shape of polysilicon element 15 and also because of the relative sizes of n-wells 10a, 10b. As shown in FIG. 1b, polysilicon element 15 has three “fingers” overlying n-well 10b, but only a single shorter length overlying n-well 10a. This difference in underlying area establishes the difference in capacitance between tunneling capacitor 4 and coupling capacitor 6.
In operation, the state stored by conventional memory cell 1 is programmed and erased by differential voltages applied to terminals P and T. The bulk of any differential voltage across terminals P and T appears as a voltage drop across tunneling capacitor 4, because of the much larger capacitance of coupling capacitor 6 relative to tunneling capacitor 4. Therefore, to “program” transistor 2 by trapping electrons on floating gate FG, the voltages applied to the terminals of memory cell are:
Terminal PTerminal T Terminal DTerminal S+Vp0 v0 v0 vwhere +Vp is a relatively high voltage (e.g., +12 to 15 volts). Because the differential voltage +Vp mostly couples to floating gate FG, a relatively high voltage (approaching voltage Vp) is established across tunneling capacitor 4. If this voltage is sufficiently high to enable electrons to tunnel through dielectric layer 20, and because polysilicon element 15 is at a positive voltage relative to p-diffusion 12a and n-well 10a, electrons will tunnel from these structures to polysilicon element 15. Upon removal of this programming bias condition, those electrons will remain trapped on the electrically isolated polysilicon element 15.
Conversely, memory cell 1 is erased by removing trapped electrons from polysilicon element 15. This is accomplished by the bias condition:
Terminal PTerminal T Terminal DTerminal S0 v+Ve0 v0 vwhere +Ve is some relatively large voltage (e.g., +12 to 15 volts) of positive polarity relative to ground (at terminal P). Again, because of the differences in capacitance between tunneling capacitor 4 and coupling capacitor 6, polysilicon element 15 is at a potential that is relatively close to ground. Because the voltage at n-well 10a and p-diffusion 12a is high relative to that of polysilicon element 15, the electrons that were trapped on polysilicon element 15 can tunnel through dielectric layer 20 to n-well 10a and p-diffusion 12a. This “erased” state remains after removal of bias, because of the electrical isolation of floating gate FG.
The state of memory cell 1 is read by applying the bias condition:
Terminal PTerminal T Terminal DTerminal S0 v0 vVD0 vwhere drain voltage VD establishes a sufficient drain-to-source voltage to enable drain-to-source conduction to distinguish the state of memory cell 1. The specific level of drain voltage VD depends on the characteristics of transistor 2, on the desired level of drain-to-source current, and on the available voltages within the integrated circuit. In this conventional approach, if electrons are trapped on polysilicon element 15 (memory cell 1 is programmed), these electrons will effectively raise the threshold voltage (or, if preferred, reduce the gate potential of transistor 2 relative to the source voltage) so that no drain-to-source conduction occurs. Conversely, if electrons are not trapped on polysilicon element 15 (memory cell 1 is erased), the absence of electrons will result in a lower threshold voltage (or a higher gate potential), specifically a threshold voltage that enables source-drain conduction through transistor 2 under these bias conditions. The presence and absence of source-drain conduction through transistor 2 thus indicates whether memory cell 1 is programmed or is erased.
While memory cell 1 provides non-volatile data storage in a structure that can be constructed by a relatively simple process technology (i.e., single polysilicon), this construction of memory cell 1 is quite costly in terms of integrated circuit chip area. The chip area required for memory cell 1 is substantial considering that three separate components (transistor 2, tunneling capacitor 4, and coupling capacitor 6) must be provided in each memory cell 1. In addition, because the programming and erase operations described above apply relatively large differential voltages, good electrical isolation must be maintained between those structures. As shown in FIG. 1b for this example, this electrical isolation is accomplished by enforcing a minimum distance dwell between n-wells 10a, 10b, and also on the other three sides of each of n-wells 10a, 10b relative to structures in neighboring memory cells. This minimum well spacing dwell may also be impacted, in some cases, by the required spacing dSD between n-well 10a (and also n-well 10b, if applicable) and the moat region within p-well 18 at which the diffusions 14c, 14d of transistor 2 are formed. This spacing dSD is determined by the ability of field oxide structures 16 (FIG. 1c) to isolate surface conduction between n-well 10a and these p-type diffusions 14c, 14d. Depending on the particular geometry of the device, if the sum of two instances of this spacing dSD (i.e., on either side of transistor 2) and the channel width of transistor 2 may exceed the well-to-well spacing dwell, then the well-to-moat spacing dSD may be the defining feature in establishing the chip area required for memory cell 1, and thus the entire EEPROM array.